1. Field of the Invention
This invention relates to the field of image processing systems, and in particular to image processing systems for use in multi-beam inspection of semiconductor wafers and masks.
2. Description of the Related Art
Image processing computers and inspection systems have been developed for semiconductor wafer and mask inspection. These wafer and mask inspection systems generally have only one imaging probe, and consequently the image processing systems used to identify defects are designed to manipulate sequential or serial data. Inspection systems with only one probe are currently only able to inspect semiconductor wafers at a rate approaching one hundredth of the processing rate of the wafers in a state-of-the-art semiconductor fabrication facility. There is a need for semiconductor wafer inspection systems with much higher throughput. One approach to achieving higher throughput is to use many imaging probes in parallel on the wafer; this then requires an image processing computer designed to accept parallel image data input and to do defect analysis in a parallel mode.
This invention includes an image processing system with a novel, highly parallel architecture. The image processing system can be used in the inspection of semiconductor wafers and masks. Image processing systems can be combined in parallel, as required. According to aspects of the invention, the image processing system comprises: a buffer memory array for acquiring raw image data and processed image data; a multiplicity of asynchronous symmetrical image processors (ASIPs) connected to the buffer memory array, each of the ASIPs being a self-contained image processor for independently performing image cross-correlation and defect detection on image data from equivalent areas of different die on a semiconductor wafer. The image processing system may further comprise one or more of the following: an image normalization engine connected to the buffer memory array, for normalizing image contrast and brightness so as to facilitate die to die image comparison as performed by the multiplicity of ASIPs; a multiplicity of parallel data channels connected to the buffer memory array, for delivering raw image data to the buffer memory array; a defect map memory connected to the multiplicity of ASIPs, for storing a map of defects as identified by an algorithm programmed into the multiplicity of ASIPs; a histogram data link connected to the image normalization engine, for delivering raw image data; and, a cross-correlation memory connected to the multiplicity of ASIPs, for storing pattern block offset data. In preferred embodiments the buffer memory array is divided into three independently and simultaneously addressable memory blocks, such that there is simultaneous access for raw image data input, normalization, and cross-correlation and defect detection. In preferred embodiments the image normalization engine comprises histogram tabulation engines connected to the histogram data link, for real-time generation of histograms of raw image data.
For the inspection of semiconductor wafers and masks, the image processing system is part of a novel inspection system, with a highly parallel architecture. According to further aspects of the invention, the inspection system, configured for a semiconductor wafer patterned with an array of identical die, comprises: an array of modules, each module comprising a probe forming system and a detector, the array comprising a multiplicity of module rows, the array of die on the wafer being aligned with the module rows; a multiplicity of image processing systems; and, a multiplicity of parallel data channels connecting the detectors with the processing systems. In different embodiments, the modules can comprise electron, charged particle or light probe forming systems. In a preferred embodiment, there is one image processing system dedicated to each row of modules. The inspection system may further comprise an inspection image display module connected to the multiplicity of image processing systems.
Further aspects of the invention including a method for semiconductor wafer defect detection comprising the steps of: acquiring raw image data from the wafer; simultaneous to the acquiring step, normalizing image data for contrast and brightness; and simultaneous to the acquiring and normalizing steps, performing cross-correlation and defect detection on normalized image data. Preferred embodiments of the method for defect detection include implementation of the performing step by a multiplicity of ASIPs. The method for defect detection may further comprise one or more of the following: ASIPs which utilize a pattern block inspection sequence designed to minimize the time required to complete cross-correlation; and simultaneous to the performing step, taking data from a cross-correlation memory, for establishing an efficient starting point for cross-correlation.
A further method of the invention utilizes a buffer memory array divided into three independently and simultaneously addressable memory blocks (A, B and C). In this method, data acquisition, data normalization, and cross correlation and defect detection utilize the buffer memory array continuously, although the buffer memory accessed (A, B or C) changes in a cyclic mode at constant time intervals; following the processing in one buffer memory: the raw image data is acquired, this image data is then normalized, this normalized data is accessed for cross-correlation and defect detection, new raw image data is acquired, etc. continuing in a cyclic mode until all the image data for a wafer has been acquired and processed.